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Central processing unit
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#	Item
991	Wshp. on Memory Performance Issues, Intl. Symp. on Computer Architecture, June[removed]Speculative Locks for Concurrent Execution of Critical Sections in Shared-Memory Multiprocessors Jose´ F. Mart´ınez and Josep Torre Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2003-12-19 18:12:59 Computer hardware Central processing unit Threads Microprocessors Lock Non-blocking algorithm Simultaneous multithreading Parallel computing Critical section Concurrency control Computing Computer architecture
992	Prof. Dr.-Ing. Dr. h. c. mult. P. J. Kühn Prof. Dr.-Ing. Dr. h. c. mult. P. J. Kühn International Symposium on Memory Management June 10–11, 2006 Ottawa, Canada Add to Reading List Source URL: www.cs.technion.ac.il Language: English - Date: 2010-02-20 10:44:16 Computing Pointer Garbage collection Classic RISC pipeline Microarchitecture Processor register CPU cache Instruction set Memory barrier Computer hardware Computer architecture Central processing unit
993	Tedd F. Sperling 600 Bluebell Drive Lansing, MI [removed] Résumé Add to Reading List Source URL: sperling.com Language: English - Date: 2012-02-23 13:20:06 Central processing unit Data model Ring STATISTICA Macintosh Embedded system Fuzzy logic Computing Software Computer architecture
994	Alpha[removed]EV6 Microprocessor Hardware Reference Manual Order Number: DS–0027C–TE This manual is directly derived from the internal[removed]EV6 Specifications, Revision 4.5. You can access this hardware reference manu Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:04:20 Computer engineering DEC Alpha PALcode Alpha 21264 CPU cache Branch predictor Processor register Instruction set Computer architecture Computer hardware Central processing unit
995	BulkSMT: Designing SMT Processors for Atomic-Block Execution∗ Xuehai Qian, Benjamin Sahelices and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Abstract Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2012-01-18 11:44:30 Computer architecture Central processing unit Parallel computing Microprocessors CPU cache Simultaneous multithreading Multithreading Computing Computer hardware Threads
996	Prototyping Architectural Support for Program Rollback: An Application to Software Debugging Radu Teodorescu and Josep Torrellas University of Illinois at Urbana-Champaign Several recently-proposed architectural techniqu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-03-04 16:59:35 Central processing unit Microprocessors Josep Torrellas Speculative execution Debugging Microarchitecture Kernel Computer program Compiler Computing Computer architecture Computer hardware
997	Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation ˜ ´ Garzar´an, Milos Prvulovic, V´ıctor Vinals Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2003-09-29 23:57:21 Central processing unit Computer memory CPU cache Cache Parallel computing Hazard Superscalar Stack Computing Computer hardware Computer architecture
998	IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING (TDSC) 1 Using Register Lifetime Predictions to Protect Register Files Against Soft Errors Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2008-08-29 19:16:16 Central processing unit Computer memory Register renaming CPU cache Register file Branch predictor Parity bit Processor register 64-bit Computer architecture Computer hardware Computing
999	Tasking with Out-of-Order Spawn in TLS Chip Multiprocessors: Microarchitecture and Compilation∗ Jose Renau† James Tuck Wei Liu Luis Ceze Karin Strauss Josep Torrellas † Dept. of Computer Engineering, University of Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-09-06 12:30:36 Central processing unit Parallel computing Classes of computers Microprocessors Superscalar Microarchitecture Speculative multithreading SPECint Coprocessor Computing Computer hardware Computer architecture
1000	CAVA: Using Checkpoint-Assisted Value Prediction to Hide L2 Misses LUIS CEZE, KARIN STRAUSS, JAMES TUCK, and JOSEP TORRELLAS University of Illinois at Urbana–Champaign and JOSE RENAU Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-27 00:10:17 Central processing unit Computer memory Runahead Cache CPU cache Branch predictor Microarchitecture Memory hierarchy Speculative execution Computer architecture Computer hardware Computer engineering

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